Input your RISC-V code here:

.asc



The most recent instructions will be shown here when stepping.

Features

  • Reset to load the code, Step one instruction, or Run all instructions
  • Set a breakpoint by clicking on the line number (only for Run)
  • View registers on the right, memory on the bottom of this page

Supported Instructions

  • Arithmetics: ADD, ADDI, SUB
  • Logical: AND,ANDI,OR,ORI, XOR,XORI
  • Sets: SLT, SLTI, SLTU, SLTIU
  • Shifts: SRA, SRAI, SRL, SRLISLL, SLLI
  • Memory: LW, SW, LB, SB
  • PC: LUI, AUIPC
  • Jumps: JAL, JALR
  • Branches: BEQ, BNE,BLT, BGE, BLTU, BGEU
  • Custom Opcodes: ERROR

RISC-V Reference: riscv-spec-v2.2.pdf

Init Value Register Decimal Hex Binary
0 Program Counter 0 0x00000000 0b00000000000000000000000000000000
0 x0 (zero) 0 0x00000000 0b00000000000000000000000000000000
x1 (ra) 0 0x00000000 0b00000000000000000000000000000000
x2 (sp) 0 0x00000000 0b00000000000000000000000000000000
x3 (gp) 0 0x00000000 0b00000000000000000000000000000000
x4 (tp) 0 0x00000000 0b00000000000000000000000000000000
x5 (t0) 0 0x00000000 0b00000000000000000000000000000000
x6 (t1) 0 0x00000000 0b00000000000000000000000000000000
x7 (t2) 0 0x00000000 0b00000000000000000000000000000000
x8 (s0/fp) 0 0x00000000 0b00000000000000000000000000000000
x9 (s1) 0 0x00000000 0b00000000000000000000000000000000
x10 (a0) 0 0x00000000 0b00000000000000000000000000000000
x11 (a1) 0 0x00000000 0b00000000000000000000000000000000
x12 (a2) 0 0x00000000 0b00000000000000000000000000000000
x13 (a3) 0 0x00000000 0b00000000000000000000000000000000
x14 (a4) 0 0x00000000 0b00000000000000000000000000000000
x15 (a5) 0 0x00000000 0b00000000000000000000000000000000
x16 (a6) 0 0x00000000 0b00000000000000000000000000000000
x17 (a7) 0 0x00000000 0b00000000000000000000000000000000
x18 (s2) 0 0x00000000 0b00000000000000000000000000000000
x19 (s3) 0 0x00000000 0b00000000000000000000000000000000
x20 (s4) 0 0x00000000 0b00000000000000000000000000000000
x21 (s5) 0 0x00000000 0b00000000000000000000000000000000
x22 (s6) 0 0x00000000 0b00000000000000000000000000000000
x23 (s7) 0 0x00000000 0b00000000000000000000000000000000
x24 (s8) 0 0x00000000 0b00000000000000000000000000000000
x25 (s9) 0 0x00000000 0b00000000000000000000000000000000
x26 (s10) 0 0x00000000 0b00000000000000000000000000000000
x27 (s11) 0 0x00000000 0b00000000000000000000000000000000
x28 (t3) 0 0x00000000 0b00000000000000000000000000000000
x29 (t4) 0 0x00000000 0b00000000000000000000000000000000
x30 (t5) 0 0x00000000 0b00000000000000000000000000000000
x31 (t6) 0 0x00000000 0b00000000000000000000000000000000


Memory Address Decimal Hex Binary
0x00000000 0 0x00000000 0b00000000000000000000000000000000
0x00000004 0 0x00000000 0b00000000000000000000000000000000
0x00000008 0 0x00000000 0b00000000000000000000000000000000
0x0000000c 0 0x00000000 0b00000000000000000000000000000000
0x00000010 0 0x00000000 0b00000000000000000000000000000000
0x00000014 0 0x00000000 0b00000000000000000000000000000000
0x00000018 0 0x00000000 0b00000000000000000000000000000000
0x0000001c 0 0x00000000 0b00000000000000000000000000000000
0x00000020 0 0x00000000 0b00000000000000000000000000000000
0x00000024 0 0x00000000 0b00000000000000000000000000000000
Credit to Danny Qiu for the creation of the original MIPS interpreter.